1. Field of the Invention
The present invention relates to a Bi-CMOS semiconductor device.
2. Description of the Background Art
FIG. 1 is an explanatory diagram of a conventional Bi-CMOS semiconductor integrated circuit device. In the conventional Bi-CMOS semiconductor device, a CMOS circuit part 2 and a bipolar circuit part 3 are mounted in a separated relation on the same semiconductor chip 1. A power source voltage supply VC of the CMOS circuit part 2 is connected through a power supply line 5 to a power supply pad 7 which is also mounted on the semiconductor chip 1. Likewise, a power source voltage supply VC of the bipolar circuit part 3 is connected through a power supply line 4 to a power supply pad 6 mounted on the semiconductor chip 1. The power supply pads 6 and 7 are commonly connected to an external power source voltage pin 10, the pad 6 being connected via a wire 8 and the pad 7 being connected via a wire 9.
This structure allows a power source voltage from the external power source voltage pin 10 to be impressed on the power supply pads 6 and 7 through the wires 8 and 9, respectively. The power source voltage thus allowed to the power supply pads 6 and 7 is then supplied to the power source voltage supplies VC of the CMOS circuit part 2 and the bipolar circuit part 3 through the power supply lines 4 and 5, respectively. In other words, the power source voltage allowed from the external power source voltage pin 10 is commonly given to the CMOS circuit part 2 and the bipolar circuit part 3 under same conditions as power source voltages for the respective circuit parts.
As heretofore described, the conventional Bi-CMOS semiconductor device as above usually comprises only one external power source voltage pin, i.e., the pin 10, for ensuring voltage to the CMOS circuit part 2 and the bipolar circuit part 3. Hence, it is a general practice that the same power source voltage from the external power source voltage pin 10 is supplied commonly to the power source voltage supplies VC of the CMOS circuit part 2 and the bipolar circuit part 3.
The bipolar circuit part 3 consumes a relatively large power source voltage. Aiming at reducing a voltage consumed at the bipolar circuit part 3, therefore, a need often arises that the bipolar circuit part 3 is driven at a lower power source voltage than a power source voltage for the CMOS circuit part 2.
Different power source voltages to the CMOS circuit part 2 and the bipolar circuit part 3 are required not only for the above purpose but also for the purpose of efficiently inspecting a semiconductor device in a burn-in test. For example, even in a semiconductor device in which both the CMOS circuit part 2 and the bipolar circuit part 3 are driven usually at 5 volts, a 7-volt power source voltage is desired for the CMOS circuit part 2. On the other hand, a voltage to the bipolar circuit part 3 is desirably around 5 volts since a 7-volt voltage often destroys the bipolar circuit part 3.
The former need cannot be satisfied in the conventional Bi-CMOS semiconductor device because its structure does not allow that the CMOS circuit part 2 and the bipolar circuit part 3 are driven by different power source voltages at the same time. As to the latter need related to a burn-in test, only one solution opens; that is, to keep the CMOS circuit part 2 inactivated while testing the bipolar circuit part 3 or vice versa. However, this approach is labor- and time-consuming.
The difficulty as above related to a burn-in test is solved by using an external power source voltage pin for each one of the CMOS circuit part 2 and the bipolar circuit part 3. However, employing a plurality of external power source voltage pins increases the number of external terminals required in the semiconductor device accordingly, thereby degrading the integration of the device. Hence, this is not a practical approach, either.